NSF/Intel Partnership on Foundational Microarchitecture Research

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Funding Opportunity ID: 297188
Opportunity Number: 17-597
Opportunity Title: NSF/Intel Partnership on Foundational Microarchitecture Research
Opportunity Category: Discretionary
Opportunity Category Explanation:
Funding Instrument Type: Grant
Category of Funding Activity: Science and Technology and other Research and Development
Category Explanation:
CFDA Number(s): 47.070
Eligible Applicants: Others (see text field entitled “Additional Information on Eligibility” for clarification)
Additional Information on Eligibility: *Who May Submit Proposals: Proposals may only be submitted by the following:
-Universities and Colleges – Universities and two- and four-year colleges (including community colleges) accredited in, and having a campus located in, the US acting on behalf of their faculty members. Such organizations also are referred to as academic institutions.
Agency Code: NSF
Agency Name: National Science Foundation
Posted Date: Sep 08, 2017
Close Date: Jan 12, 2018
Last Updated Date: Sep 08, 2017
Award Ceiling:
Award Floor: $500,000
Estimated Total Program Funding: $3,000,000
Expected Number of Awards:
Description: The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting Thread Level Parallelism (TLP) and Data Level Parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future. The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements to continue the cadence promised by Moore’s Law.

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