Electronics Resurgence Initiative: Page 3 Investments Architectures Thrust

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Funding Opportunity ID: 297375
Opportunity Number: HR001117S0055
Opportunity Title: Electronics Resurgence Initiative: Page 3 Investments Architectures Thrust
Opportunity Category: Discretionary
Opportunity Category Explanation:
Funding Instrument Type: Cooperative Agreement
Grant
Other
Procurement Contract
Category of Funding Activity: Science and Technology and other Research and Development
Category Explanation:
CFDA Number(s): 12.910
Eligible Applicants: Unrestricted (i.e., open to any type of entity above), subject to any clarification in text field entitled “Additional Information on Eligibility”
Additional Information on Eligibility:
Agency Code: DOD-DARPA-MTO
Agency Name: Department of Defense
DARPA – Microsystems Technology Office
Posted Date: Sep 13, 2017
Close Date: The full proposal must be submitted via the DARPA BAA website on or before 1:00 PM, Eastern Time, December 4, 2017. If deemed compliant, the Government will evaluate all such proposals in the initial round of selections. Additionally, proposals may be submitted after the above due date until 1:00 PM, Eastern Time, January 31, 2018 which, if deemed compliant, will be reviewed at the Government’s discretion, depending upon the availability of funding. Proposers are warned that the likelihood of available funding is greatly reduced for proposals submitted after the initial closing date deadline.
Last Updated Date: Sep 13, 2017
Award Ceiling:
Award Floor:
Estimated Total Program Funding:
Expected Number of Awards:
Description: DARPA is soliciting innovative research proposals in the area of novel computing architectures. The Page 3 Architectures thrust of the Electronics Resurgence Initiative (ERI) seeks to demonstrate heterogeneous computing systems that provide the performance advantages of specialized processors, while maintaining the programmability of general purpose processors. The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near ASIC performance without sacrificing programmability for data-intensive algorithms. SDH will create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time or single application limitations associated with ASIC development. The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable rapid development of multi-application systems through a single programmable device.
Version: Synopsis 1





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